View LTC2453CTS8PBF_6276120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2453 1 2453fc differential input voltage (v) ?3 inl (lsb) ?0.5 0 0.5 0 2 2453 ta01b ?1.0 ?1.5 ?2.0 ?2 ?1 1 1.0 1.5 2.0 3 v cc = 3v v ref + = 3v v ref ? = 0v t a = ?45c, 25c, 90c typical application features description ultra-tiny, differential, 16-bit ds adc with i 2 c interface the ltc ? 2453 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. the ltc2453 uses a single 2.7v to 5.5v supply and communicates through an i 2 c interface. the adc is available in an 8-pin, 3mm 2mm dfn package or 8-pin, 3mm 3mm tsot package. it includes an integrated oscillator that does not require any external components. it uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. the ltc2453 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude lower than conventional delta-sigma converters. additionally, due to its architecture, there is negligible current leakage between the input pins. the ltc2453 can sample at 60 conversions per second, and due to the very large oversampling ratio, has ex-tremely relaxed antialiasing requirements. the ltc2453 includes continuous internal offset and full-scale calibration algo - rithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. the converter has external ref + and ref C pins and the differen - tial input voltage range can extend up to (v ref + C v ref C ). following a single conversion, the ltc2453 can auto-matically enter a sleep mode and reduce its power to less than 0.2a. if the user reads the adc once a second, the ltc2453 con - sumes an average of less than 50w from a 2.7v supply. v cc differential input range 16-bit resolution (including sign), no missing codes 2lsb offset error 4lsb full-scale error 60 conversions per second single conversion settling time for multiplexed applications single-cycle operation with auto shutdown 800a supply current 0.2a sleep current internal oscillatorno external components required 2-wire i 2 c interface ultra-tiny 8-pin 3mm 2mm dfn and tsot23 packages applications system monitoring environmental monitoring direct temperature measurements instrumentation industrial process control data acquisition embedded adc upgrades 10k 10k 10k r scl 2-wire i 2 c interface sda 0.1f 0.1f 10f 2.7v to 5.5v 0.1f in + ref + v cc ref ? gnd in ? ltc2453 2453 ta01 integral nonlinearity, v cc = 3v l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. no latency ds is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6208279, 6411242, 7088280, 7164378.
ltc2453 2 2453fc absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v analog input voltage (v in + , v in C ) .. C0.3v to (v cc + 0.3v) reference voltage (v ref + , v ref C ) .. C0.3v to (v cc + 0.3v) digital voltage (sda, scl) ............ C0.3v to (v cc + 0.3v) (notes 1, 2) pin configuration order information electrical characteristics parameter conditions min typ max units resolution (no missing codes) (note 3) l 16 bits integral nonlinearity (note 4) l 2 10 lsb offset error l 2 10 lsb offset error drift 0.02 lsb/c gain error l 0.01 0.02 % of fs gain error drift 0.02 lsb/c transition noise 1.4 v rms power supply rejection dc 80 db the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 2) storage temperature range ................... C65c to 150c operating temperature range ltc2453c ................................................ 0c to 70c ltc2453i .............................................. C40c to 85c top view 9 ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1gnd ref ? ref + v cc sda scl in + in ? c/i grade t jmax = 125c, ja = 76c/w exposed pad (pin 9) is gnd, must be soldered to pcb gnd 1 ref 2 ref + 3 v cc 4 8 sda 7 scl 6 in + 5 in top view ts8 package 8-lead plastic tsot-23 c/i grade t jmax = 125c, ja = 140c/w lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2453cddb#trmpbf ltc2453cddb#trpbf ldbq 8-lead plastic (3mm 2mm) dfn 0c to 70c ltc2453iddb#trmpbf ltc2453iddb#trpbf ldbq 8-lead plastic (3mm 2mm) dfn C40c to 85c ltc2453cts8#trmpbf ltc2453cts8#trpbf ltdcg 8-lead plastic tsot-23 0c to 70c ltc2453its8#trmpbf ltc2453its8#trpbf ltdcg 8-lead plastic tsot-23 C40c to 85c trm = 500 pieces. *temperature grades are identifed by a label on the shipping container. consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc2453 3 2453fc the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 2, 7) analog inputs and references symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion sleep l l 800 0.2 1200 0.6 a a power requirements symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v i i digital input current l C10 10 a v hys hysteresis of schmidt trigger inputs (note 3) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v i in input leakage 0.1v cc v in 0.9v cc l 1 a c i capacitance for each i/o pin l 10 pf c b capacitance load for each bus line l 400 pf i 2 c inputs and outputs symbol parameter conditions min typ max units v in + positive input voltage range l 0 v cc v v in C negative input voltage range l 0 v cc v v ref + positive reference voltage range v ref + C v ref C 2.5v l v cc C 2.5 v cc v v ref C negative reference voltage range v ref + C v ref C 2.5v l 0 v cc C 2.5 v v or + + v ur + overrange + underrange voltage, in + v ref = 5v, v in C = 2.5v (see figure 2) 31 lsb v or C + v ur C overrange + underrange voltage, inC v ref = 5v, v in + = 2.5v (see figure 2) 31 lsb c in in + , in C sampling capacitance 0.35 pf i dc_leak(in + ) in + dc leakage current v in = gnd (note 8) v in = v cc (note 8) l l C10 C10 1 1 10 10 na na i dc_leak(in C ) in C dc leakage current v in = gnd (note 8) v in = v cc (note 8) l l C10 C10 1 1 10 10 na na i dc_leak(ref + , ref C ) ref + , ref C dc leakage current v ref = 3v (note 8) l C10 1 10 na i conv input sampling current (note 5) 50 na
ltc2453 4 2453fc typical performance characteristics integral nonlinearity, v cc = 5v integral nonlinearity, v cc = 3v maximum inl vs temperature the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 2, 7) symbol parameter conditions min typ max units t conv conversion time l 13 16.6 23 ms f scl scl clock frequency l 0 400 khz t hd(sda) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda, scl signals (note 6) l 20 + 0.1c b 300 ns t f fall time for sda, scl signals (note 6) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s t of output fall time v ihmin to v ilmax bus load c b 10pf to 400pf (note 6) l 20 + 0.1c b 250 ns t sp input spike suppression l 50 ns i 2 c timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltage values are with respect to gnd. v cc = 2.7v to 5.5v unless otherwise specifed. v ref = v ref + C v ref C , v refcm = (v ref + + v ref C )/2, fs = v ref + C v ref C ; v in = v in + C v in C , Cv ref v in v ref ; v incm = (v in + + v in C )/2. note 3. guaranteed by design, not subject to test. note 4. integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. guaranteed by design and test correlation. note 5. input sampling current is the average input current drawn from the input sampling network while the ltc2453 is converting. note 6. c b = capacitance of one bus line in pf. note 7. all values refer to v ih(min ) and v il(max) levels. note 8. a positive current is fowing into the dut pin. differential input voltage (v) ?5 inl (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 3 2453 g01 ?3 ?1 1 5 2 ?4 ?2 0 4 v cc = 5v v ref + = 5v v ref ? = 0v t a = ?45c, 25c, 90c differential input voltage (v) ?3 inl (lsb) ?0.5 0 0.5 0 2 2453 g02 ?1.0 ?1.5 ?2.0 ?2 ?1 1 1.0 1.5 2.0 3 v cc = 3v v ref + = 3v v ref ? = 0v t a = ?45c, 25c, 90c temperature (c) ?50 0 inl (lsb) 0.5 1.0 1.5 2.0 ?25 0 25 50 2453 g03 75 100 v cc = v ref + = 5v, 4.1v, 3v (t a = 25c, unless otherwise noted)
ltc2453 5 2453fc offset error vs temperature gain error vs temperature transition noise vs temperature transition noise vs output code conversion mode power supply current vs temperature sleep mode power supply current vs temperature typical performance characteristics average power dissipation vs temperature, v cc = 3v power supply rejection vs frequency at v cc conversion time vs temperature temperature (c) ?50 ?1 offset error (lsb) 0 1 2 3 5 ?25 0 25 50 2453 g04 75 100 4 v cc = v ref + = 3v v cc = v ref + = 5v v cc = v ref + = 4.1v temperature (c) ?50 0 gain error (lsb) 1 2 3 4 5 ?25 0 25 50 2453 g05 75 100 v cc = v ref + = 3v v cc = v ref + = 5v v cc = v ref + = 4.1v temperature (c) ?50 0 transition noise rms (v) 0.5 1.0 1.5 2.0 3.0 ?25 0 25 50 2453 g06 75 100 2.5 v cc = 4.1v v cc = 5v v cc = 3v output code ?32768 32768 0 transition noise rms (v) 0.5 1.0 1.5 2.0 ?16384 16384 0 2453 g07 2.5 3.0 v cc = v ref + = 3v v cc = v ref + = 5v temperature (c) ?50 0 conversion current (a) 200 400 600 800 1200 ?25 0 25 50 2453 g08 75 100 1000 v cc = 5v v cc = 3v v cc = 4.1v 60hz output sample rate temperature (c) ?50 0 sleep current (na) 50 100 150 200 250 ?25 0 25 50 2453 g09 75 100 v cc = 5v v cc = 3v v cc = 4.1v temperature (c) ?50 1 average power dissipation (w) 10 100 1000 10000 ?25 0 25 50 2453 g10 75 100 25hz output sample rate 10hz output sample rate 1hz output sample rate frequency at v cc (hz) 1 10 ?100 rejectioin (db) ?60 0 100 10k 100k 2453 g11 ?80 ?20 ?40 1k 1m 10m v cc = 4.1v v ref + = 2.7v v ref ? = 0v v in + = 1v v in ? = 2v temperature (c) ?50 21 20 19 18 17 16 15 14 25 75 2453 g12 ?25 0 50 100 conversion time (ms) v cc = 3v v cc = 5v v cc = 4.1v (t a = 25c, unless otherwise noted)
ltc2453 6 2453fc block diagram pin functions gnd (pin 1): ground. connect to a ground plane through a low impedance connection. ref C (pin 2), ref + (pin 3): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref C , by at least 2.5v. the differential reference voltage (v ref = ref + to ref C ) sets the full-scale range. v cc (pin 4): positive supply voltage. bypass to gnd (pin 1) with a 10f capacitor in parallel with a low-series- inductance 0.1f capacitor located as close to the part as possible. in C (pin 5), in + (pin 6): differential analog input. scl (pin 7): serial clock input of the i 2 c interface. the ltc2453 can only act as a slave and the scl pin only ac - cepts external serial clock. data is shifted into the sda pin on the rising edges of scl and output through the sda pin on the falling edges of scl. sda (pin 8): bidirectional serial data line of the i 2 c interface. the conversion result is output through the sda pin. the pin is high impedance unless the ltc2453 is in the data output mode. while the ltc2453 is in the data output mode, sda is an open drain pull down (which requires an external 1.7k pull-up resistor to v cc ). exposed pad (pin 9, dfn only): ground. must be soldered to pcb ground. 16-bit ? a/d converter decimating sinc filter scl ref + v cc ref ? in + in ? gnd sda 2453 bd ? 16-bit ? a/d converter i 2 c interface internal oscillator 3 4 7 8 1 2 6 5
ltc2453 7 2453fc converter operation converter operation cycle the ltc2453 is a low-power, fully differential, delta-sigma analog-to-digital converter with an i 2 c interface. its oper - ation, as shown in figure 1, is composed of three suc - cessive states: conversion, sleep and data output. initially, at power up, the ltc2453 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by several orders of magnitude. the part remains in the sleep state as long as it is not addressed for a read operation. the conversion result is held indefnitely in a static shift register while the part is in the sleep state. applications information edges of scl, allowing the user to reliably latch data on the rising edge of scl. a new conversion is initiated by a stop condition following a valid read operation, or by the conclusion of a complete read cycle (all 16 bits read out of the device). power-up sequence when the power supply voltage (v cc ) applied to the con- verter is below approximately 2.1v, the adc performs a power-on reset. this feature guarantees the integrity of the conversion result. when v cc rises above this threshold, the converter gener - ates an internal power-on reset (por) signal for approxi - mately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2453 starts a conversion cycle and follows the succession of states described in figure 1. the frst conversion result following por is ac - curate within the specifcations of the device if the power supply voltage v cc is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. ease of use the ltc2453 data output has no latency, flter settling delay or redundant results associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog input voltages requires no special actions. the ltc2453 performs offset calibrations every conver - sion. this calibration is transparent to the user and has no effect upon the cyclic operation described previ - ously. the advantage of continuous calibration is extreme stability of the adc performance with respect to time and temperature. the ltc2453 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. this allows external flter networks to in - terface directly to the ltc2453. since the average input sampling current is 50na, an external rc lowpass flter using a 1k and 0.1f results in <1lsb additional error. additionally, there is negligible leakage current between in + and in C . read acknowledge data output yes yes 2453 f01 stop or read 16-bits sleep conversion power-on reset no no figure 1. ltc2453 state diagram the device will not acknowledge an external request during the conversion state. after a conversion is fnished, the device is ready to accept a read request. the ltc2453s address is hard-wired at 0010100. once the ltc2453 is addressed for a read operation, the device begins output - ting the conversion result under the control of the serial clock (scl). there is no latency in the conversion result. the data output is 16 bits long and contains a 15-bit plus sign conversion result. data is updated on the falling
ltc2453 8 2453fc reference voltage range this converter accepts a truly differential external reference voltage. the absolute/common mode voltage range for ref + and ref C pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref + must be >(2.5v + v ref C ). the ltc2453 differential reference input range is 2.5v to v cc . for the simplest operation, ref + can be shorted to v cc and ref C can be shorted to gnd. input voltage range for most applications, v ref C (v in + , v in C ) v ref + . under these conditions the output code is given (see data format section) as 32768 ? (v in + C v in C )/(v ref + C v ref C ) + 32768. the output of the ltc2453 is clamped at a minimum value of 0 and clamped at a maximum value of 65535. the ltc2453 includes a proprietary system that can, typically, correctly digitize each input 8lsb above v ref + and below v ref C , if the ltc2453s output is not clamped. as an example (figure 2), if the user desires to measure a signal slightly below ground, the user could set v in C = v ref C = gnd, and v ref + = 5v. if v in + = gnd, the output code would be approximately 32768. if v in + = gnd C 8lsb = C1.22 mv, the output code would be approximately 32760. the total amount of overrange and underrange capability is typically 31lsb for a given device. the 31lsb total is distributed between the overrange and underrange capability. for example, if the underrange capability is 8lsb, the overrange capability is typically 31 C 8 = 23lsb. i 2 c interface the ltc2453 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. the con - nected devices can only pull the data line (sda) low and never drive it high. sda must be externally connected to the supply through a pull-up resistor. when the data line is free, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard-mode and up to 400kbits/s in the fast-mode. the v cc power should not be removed from the device when the i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. devices addressed by the master are considered a slave. the address of the ltc2453 is 0010100. the ltc2453 can only be addressed as a slave. it can only transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2453 and the serial data line sda is bidirectional. figure 3 shows the defnition of the i 2 c timing. the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is consid - ered to be busy after the start condition. when the data transfer is fnished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated v in + /v ref + ?0.001 output code 32772 32780 32788 0.001 2453 f02 32764 32756 32768 32776 32784 32760 32752 32748 ?0.005 0 0.005 0.0015 signals below gnd figure 2. output code vs v in + with v in C = 0 and v ref C = 0 applications information
ltc2453 9 2453fc start timing is functionally identical to the start and is used for reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nak) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. data format after a start condition, the master sends a 7-bit address followed by a read request (r) bit. the bit r is 1 for a read request. if the 7-bit address matches the ltc2453s address (hard-wired at 0010100) the adc is selected. when the device is addressed during the conversion state, it does not accept the request and issues a nak by leaving the sda line high. if the conversion is complete, the ltc2453 issues an ack by pulling the sda line low . following the ack, the ltc2453 can output data. the data output stream is 16 bits long and is shifted out on the falling edges of scl (see figure 4). the frst bit output by the ltc2453, the msb, is the sign, which is 1 for v in + v in C and 0 for v in + < v in C (see table 1). the msb (d15) is followed by successively less signifcant bits (d14, d13) until the lsb is output by the ltc2453. this sequence is shown in figure 5. operation sequence continuous read conversions from the ltc2453 can be continuously read, see figure 6. at the end of a read operation, a new conversion automatically begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not complete and a valid address selects the device, the ltc2453 generates a nak signal indicating the conversion cycle is in progress. discarding a conversion result and initiating a new conversion it is possible to start a new conversion without reading the old result, as shown in figure 7. following a valid 7-bit address, a read request (r) bit, and a valid ack, a stop command will start a new conversion. preserving the converter accuracy the ltc2453 is designed to dramatically reduce the conver - sion results sensitivity to device decoupling, pcb layout, antialiasing circuits, line and frequency perturbations. nevertheless, in order to preserve the high accuracy capa - bility of this part, some simple precautions are desirable. digital signal levels due to the nature of cmos logic, it is advisable to keep input digital signals near gnd or v cc . voltages in the range of 0.5v to v cc C 0.5v may result in additional cur - rent leakage from the part. sda scl s sr p s t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2453 f03 figure 3. defnition of timing for fast/standard mode devices on the i 2 c bus applications information
ltc2453 10 2453fc sleep 7-bit address (0010100) s p r ack read data output conversion conversion 2453 f05 figure 5. the ltc2453 coversion sequence sleep sleep s p r ack read read data output conversion conversion 2453 f06 s r p ack conversion data output 7-bit address (0010100) 7-bit address (0010100) figure 6. consecutive reading at the same confguration figure 7. start a new conversion without reading old conversion result sleep s p r ack read (optional) data output conversion conversion 2453 f07 7-bit address (0010100) applications information 1 7 8 9 2 3 1 8 d8 d13d14 (sgn) msb d15 r sda scl 7-bit address start by master d7 d6 d5 d0 lsb 9 1 2 3 8 9 ack by ltc2453 ack by master nack by master sleep data output conversion 2453 f04 figure 4. read sequence timing diagram table 1. ltc2453 output data format. fs = v ref + C v ref - . differential input voltage v in + - v in - d15 (msb) d14 d13 d12 ... d2 d1 d0 (lsb) corresponding decimal value fs 1 1 1 1 1 1 65535 fs - 1lsb 1 1 1 1 1 0 65534 0.5 ? fs 1 1 0 0 0 0 49152 0.5 ? fs - 1lsb 1 0 1 1 1 1 49151 0 1 0 0 0 0 0 32768 -1lsb 0 1 1 1 1 1 32767 -0.5 ? fs 0 1 0 0 0 0 16384 -0.5 ? fs - 1lsb 0 0 1 1 1 1 16383 -fs 0 0 0 0 0 0 0
ltc2453 11 2453fc driving v cc and gnd in relation to the v cc and gnd pins, the ltc2453 com - bines internal high frequency decoupling with damping elements, which reduce the adc performance sensitivity to pcb layout and external components. nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the v cc and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc package. it is also desirable to avoid any via in the circuit path, starting from the converter v cc pin, passing through these two decoupling capacitors, and returning to the converter gnd pin. the area encompassed by this circuit path, as well as the path length, should be minimized. very low impedance ground and power planes, and star connections at both v cc and gnd pins, are preferable. the v cc pin should have three distinct connections: the frst to r sw 15k (typ) i leak i leak v cc v cc v cc v cc c eq 0.35pf (typ) in + in ? ref ? ref + 2453 f08 r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak figure 8. ltc2453 analog input/reference equivalent circuit i leak i leak r sw 15k (typ) i conv c in in + v cc sig + sig ? r s c eq 0.35pf (typ) c par + ? 2453 f09 i leak i leak r sw 15k (typ) i conv c in in ? v cc r s c eq 0.35pf (typ) c par + ? figure 9. ltc2453 input drive equivalent circuit the decoupling capacitors described above, the second to the ground return for the input signal source, and the third to the ground return for the power supply voltage source. driving ref + and ref C a simplifed equivalent circuit for ref + and ref C is shown in figure 8. like all other a/d converters, the ltc2453 is only as accurate as the reference it is using. therefore, it is important to keep the reference line quiet by careful low and high frequency power supply decoupling. the lt6660 reference is an ideal match for driving the ltc2453s ref + pin. the ltc6660 is available in a 2mm 2mm dfn package with 2.5v, 3v, 3.3v and 5v options. a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the ref + /ref C and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc. driving v in + and v in C the input drive requirements can best be analyzed using the equivalent circuit of figure 9. the input signal v sig is connected to the adc input pins (in + and in C ) through an equivalent source resistance r s . this resistor includes both the actual generator source resistance and any ad - ditional optional resistors connected to the input pins. optional input capacitors c in are also connected to the applications information
ltc2453 12 2453fc adc input pins. this capacitor is placed in parallel with the adc input parasitic capacitance c par . depending on the pcb layout, c par has typical values between 2pf and 15pf. in addition, the equivalent circuit of figure 9 includes the converter equivalent internal resistor r sw and sampling capacitor c eq . there are some immediate trade-offs in r s and c in without needing a full circuit analysis. increasing r s and c in can give the following benefts: 1) due to the ltc2453s input sampling algorithm, the input current drawn by either v in + or v in C over a con - version cycle is 50na. a high r s ? c in attenuates the high frequency components of the input current, and r s values up to 1k result in <1lsb error. 2) the bandwidth from v sig is reduced at the input pins (in + , in C ). this bandwidth reduction isolates the adc from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) switching transients generated by the adc are attenu - ated before they go back to the signal source. 4) a large c in gives a better ac ground at the input pins, helping reduce refections back to the signal source. 5) increasing r s protects the adc by limiting the current during an outside-the-rails fault condition. there is a limit to how large r s ? c in should be for a given application. increasing r s beyond a given point increases figure 10. measured inl vs input voltage, c in = 0.1f, v cc = 5v, t a = 25c the voltage drop across r s due to the input current, to the point that signifcant measurement errors exist. additionally, for some applications, increasing the r s ? c in product too much may unacceptably attenuate the signal at frequencies of interest. for most applications, it is desirable to implement c in as a high-quality 0.1f ceramic capacitor and r s 1k. this capacitor should be located as close as possible to the actual v in package pin. furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. in the case of a 2-wire sensor that is not remotely grounded, it is desirable to split r s and place series resistors in the adc input line as well as in the sensor ground return line, which should be tied to the adc gnd pin using a star connection topology. figure 10 shows the measured ltc2453 inl vs input voltage as a function of r s value with an input capacitor c in = 0.1f. in some cases, r s can be increased above these guidelines. the input current is zero when the adc is either in sleep or i/o modes. thus, if the time constant of the input rc circuit t = r s ? c in , is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. figure 11. measured inl vs input voltage, c in = 0, v cc = 5v, t a = 25c applications information differential input voltage (v) ?5 inl (lsb) 2 6 10 3 2453 f10 ?2 ?6 0 4 8 ?4 ?8 ?10 ?3?4 ?1?2 1 2 4 0 5 r s = 10k r s = 2k r s = 1k r s = 0 c in = 0.1f v cc = 5v t a = 25c differential input voltage (v) ?5 inl (lsb) 2 6 10 3 2453 f11 ?2 ?6 0 4 8 ?4 ?8 ?10 ?3?4 ?1?2 1 2 4 0 5 r s = 10k r s = 1k, 2k r s = 0 c in = 0 v cc = 5v t a = 25c
ltc2453 13 2453fc input signal frequency (mhz) 0 input signal attenuation (db) ?40 0 1.00 1.25 1.50 2453 f12 ?60 ?80 ?20 ?100 2.5 5.0 7.5 input signal frequency (hz) 0 input signal attenuatioin (db) ?20 ?10 0 480 2453 f13 ?30 ?40 ?25 ?15 ?5 ?35 ?45 ?50 12060 240180 360 420 540 300 600 figure 12. ltc2453 input signal attentuation vs frequency figure 13. ltc2453 input signal attenuation vs frequency (low frequencies) these considerations need to be balanced out by the input signal bandwidth. the 3db bandwidth 1/(2pr s c in ). finally, if the recommended choice for c in is unacceptable for the users specifc application, an alternate strategy is to eliminate c in and minimize c par and r s . in practical terms, this confguration corresponds to a low impedance sensor directly connected to the adc through minimum length traces. actual applications include current measure - ments through low value sense resistors, temperature meas urements, low impedance voltage source monitoring, and so on. the resultant inl vs v in is shown in figure 11. the measurements of figure 11 include a capacitor c par corresponding to a minimum sized layout pad and a mini- mum width input trace of about 1 inch length. signal bandwidth, transition noise and noise equivalent input bandwidth the ltc2453 includes a sinc 1 type digital flter with the frst notch located at f 0 = 60hz. as such, the 3db input signal bandwidth is 26.54hz. the calculated ltc2453 input signal attenuation vs frequency over a wide frequency range is shown in figure 12. the calculated ltc2453 input signal attenuation vs frequency at low frequencies is shown in figure 13. the converter noise level is about 1.4v rms and can be modeled by a white noise source connected at the input of a noise-free converter. on a related note, the ltc2453 uses two separate a/d converters to digitize the positive and negative inputs. each of these a/d converters has 1.4v rms transition noise. if one of the input voltages is within this small transition noise band, then the output will fuctuate one bit, regard - less of the value of the other input voltage. if both of the input voltages are within their transition noise bands, the output can fuctuate 2 bits. for a simple system noise analysis, the v in drive circuit can be modeled as a single-pole equivalent circuit character - ized by a pole location f i and a noise spectral density n i . if the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than f i , then the total noise contribution of the external drive circuit would be: v n = n i p / 2 ? f i then, the total system noise level can be estimated as the square root of the sum of (v n 2 ) and the square of the ltc2453 noise foor (~1.4v 2 ). applications information
ltc2453 14 2453fc typical application in + 7 8 r7 4.99k 1% r6 4.99k 1% 2 1 3 4 9 in ? scl 6 5 sda ref ? c8 0.1f c7 0.1f c2 0.1f v cc r1 1k e1 in + e2 in ? r9 1k c6 0.1f c3 1f c4 1f 1 lt6660 3 42 r4 1.0 c1 0.1f c10 0.1f jp1 ext 5v gnd ref + ltc2453 v cc v cc scl sda gnd nc 3 14 12 9 10 11 5 7 4 6 2 1 v + j1 to controller v cc 8 13 2453 ta02 eescl eevcc eesda eegnd cs sck/scl mosi/sda miso vunreg 5v gnd gnd gnd e3 v cc e4 gnd e6 ref ? jp2 ext gnd e5 ref + 2 1 3 7 6 sda v cc 4 8 5 scl wp a2 a1 a0 gnd 24lc025-i/st in v + out gnd gnd r8 4.99k 1% c5 0.1f c9 1f dc1266a demo board schematic
ltc2453 15 2453fc ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) package description 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc
ltc2453 16 2453fc package description tsot package 8-lead plastic tsot (reference ltc ts8 # 05-08-1637) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc2453 17 2453fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 6/10 added text to i 2 c interface section 8 c 3/11 updated analog inputs and references section add text to input voltage range section 3 8 (revision history begins at rev b)
ltc2453 18 2453fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2007 lt 0311 rev c ? printed in usa related parts part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/c drift lt1790 micropower precision reference in tsot-23-6 package 60a max supply current, 10ppm/c max drift, 1.25v, 2.048v, 2.5v, 3v, 3.3v, 4.096v and 5v options ltc1860/ltc1861 12-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 12-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 16-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2440 24-bit no latency ds tm adc 200nv rms noise, 8khz output rate, 15ppm inl ltc2480 16-bit, differential input, no latency ds adc, with pga, temp. sensor, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2481 16-bit, differential input, no latency ds adc, with pga, temp. sensor, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2482 16-bit, differential input, no latency ds adc, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2483 16-bit, differential input, no latency ds adc, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2484 24-bit, differential input, no latency ds adc, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2485 24-bit, differential input, no latency ds adc, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc6241 dual, 18mhz, low noise, rail-to-rail op amp 550nv p-p noise, 125v offset max lt6660 micropower references in 2mm 2mm dfn package, 2.5v, 3v, 3.3v, 5v 20ppm/c max drift, 0.2% max ltc2450 easy-to-use, ultra-tiny 16-bit adc 2 lsb inl, 50na sleep current, tiny 2mm 2mm dfn-6 package, 30hz output rate ltc2450-1 easy-to-use, ultra-tiny 16-bit adc 2 lsb inl, 50na sleep current, tiny 2mm 2mm dfn-6 package, 60hz output rate

▲Up To Search▲

Price & Availability of LTC2453CTS8PBF

	To Download LTC2453CTS8PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .